Peregrine II - High Performance Digital Receiver/Exciter/Software Defined Radio

Features

Stratix 10 FPGAs
  • GX280UF50 (L-tile)
  • 96 XCVR
  • 2.8M logic elements
  • 11,520 18×19 multipliers

DAC (AD9119)
  • 12-bit 5.7 GS/sec
  • LVDSx22

ADC (AD9625)
  • 12-bit 2.5 GS/sec
  • JESD204B – 8 lanes @ 6.25 Gbps

Processing FPGAs (FPGA1-4)
  • PCIe Gen3x4
  • 16 GB/s FPGA-to-FPGA crossbar
  • 30x GPIO crossbar

I/O FPGA (FPGA0)
  • PCIe Gen3x4
  • 32 GB/s FPGA-to-FPGA
  • 16 GB DDR3 with ECC
  • 2x QSFP 40GbE
  • JESD204B interface to ADCs
  • LVDS interface to DACs

SBC (COM EXPRESS INTEL i7 Kaby-Lake 7820 EQ)
  • PCIe Gen3x8 to FPGAs
  • 2x PCIe Gen3x4 slots
  • GbE
  • 2x USB 3.0
  • 1x M.2 SATA
  • 1x SATA
  • LVDS interface to DACs