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3DR Lightning I - 4-channel, 12-bit, 10 GSPS Analog-to-Digital Converter

Features

FPGA
  • FPGA Altera Arria 10
  • 10AX115U3F45I2SG
  • 2x—Hybrid Memory Cube (HMC)

Analog-to-Digital Conversion
  • 4×2.5 GSPS channels non-interleaved
  • 2×5 GSPS channels interleaved
  • 1×10 GSPS channel interleaved
  • 12-bit
  • >8 ENOB
  • Non-linear equalizer IP
  • >4 GHz instantaneous bandwidth

Clocking and Triggering Flexibility
  • Sample gates (SMA)
  • Trigger (SMA)
  • Clock inputs (SMA/TwinAx)
  • ToD—Time of Day

I/O Support Available Via:
  • Y-connector (2x)
  • Z-connector (1x)
  • High speed connector (1x Top)
  • JTAG
  • 4x—40 GbE daughter card
Lightning I with shadow

Block Diagram