3DR-V6-ADC-160MSPS

The 3DR-V6-ADC-160MSPS is a 10 channel, 16 bit, 160MHz analog-to-digital converter board for digitizing and processing analog inputs. High performance, low latency processing can be implemented via the on-board VIRTEX –6 FPGA (XC6VLX240T).

Files

Description

The 3DR-V6-ADC-160MSPS is a 10 channel, 16 bit, 160MHz Analog-to-Digital converter board for digitizing and processing analog inputs. High performance, low latency processing can be implemented via the on-board VIRTEX –6 FPGA (XC6VLX240T).

As with all 3DR Computing modules, the 3DR-V6-ADC-160MSPS supports 3 dimensional connectivity, allowing the user to stack and/or tile modules to address a wide variety of processing, I/O, size, weight, and power requirements. The 3DR-V6-ADC-160MSPS provides PCIe and LVDS interfaces via the Y and Z connectors to other modules in the 3DR Computing family. It also offers additional external interfaces including TwinAx, and SMA connections for clocking and triggering flexibility.

The 3DR-V6-ADC-160MSPS standard microcontroller architecture is interfaced through the I2C bus to provide FPGA temperature, voltage, and current monitoring for automatic shut-down during critical overheat and/or voltage conditions.

Features

Product Benefits

  • Enough FPGA Flash Memory to hold two FPGA configurations
  • On board circuitry fuse and temperature monitoring for board protection
  • Standard 4-pin power connector

FPGA

  • Xilinx Virtex 6 (XC6VLX240T)
  • DDR Memory Module
  • Up to two FPGA configurations

I/O Support Available Via:

  • Y-Connector (2x)
  • Z-Connector (2x)
  • JTAG
  • DB29 connections

Analog-to-Digital Conversion

  • 10 Channel
  • 16-bit
  • 160MSPS
  • SNR 78dB
  • SFDR 95dB

Clocking and Triggering Flexibility

  • Sample Gates (SMA)
  • Trigger (SMA)
  • Clock Inputs (SMA/TwinAx)

Applications

  • Digital Signal Processing/Data Acquisition
  • Radar Receiver (Digital Receiver)
  • Digital Array Processing & Beamforming
  • Electronic Warfare/Attack Systems
  • Digital Image Processing
  • Remote Sensing

Specifications

Standard 3DR-V6-ADC-160MSPS Microcontroller Interface

  • Dual Microcontrollers Programmable over SPI bus
  • Controls Power-on and Power-down Sequencing
  • Monitors Voltages and Reports Faults over I2C Bus
  • Monitors Current, e-fuse shut-down, and reports over I2C Bus
  • Monitors board/chip temperature over I2C Bus (external user-defined sensor available)
  • On-board EEPROM for Data Storage and Logging (write protect available)
  • FPGAs and CPLDs Programmable over JTAG Bus (for applicable modules with FPGAs and CPLDs), or via Connectors from other 3DR Computing Boards (firmware required)

FPGA

  • Xilinx, Virtex 6XC6VLX240T
  • LX365T & LX550T Available in 1759 Package
  • JTAG Programmable
  • 2 NOR Flash Configuration/User Programmable Memories (Master BPI Configuration, write protects available)

DDR2

  • Up to 3GB

A/D

  • Texas Instruments ADC 6DV160 (2 channels/device)
  • 16 Bit, 160 MHz, 160 MSPS
  • Up to 10 Channels
  • DDR LVDS Output
  • +/- 1.1v PP Input, 50 Ohm Input Impedance

Power

  • Power Consumption (based on FPGA loading) 12V @2.0 Amps

Environmental

  • Operating Temperature: 0°C to 50°C (commercial configuration)
  • Storage Temperature: (est) -55°C to 100°C, Cooling Airflow Recommended, FPGA Application Dependent (heat sink mounts available)

Clocking Options

  • On-board Oscillator
  • Off-board SMA
  • Off-board TwinAx
  • Board-to-Board Y Connector
  • Board-to-Board Z Connector

External Interfaces

  • Y1, Z1 Connectors: LVDS (FPGA)
  • Y2, Z2 Connectors: PCIe & LVDS (FPGA)
  • A/D Channels; Up to 10 25-pin D-sub General Purpose I/O

Physical

  • Dimensions: 6.25″L x 6.25″W (including connectors: 6.668″L x 6.289″W)
  • Distance Between Boards (stacked, board-to-board): 1.1″
  • Weight: ~13 oz.