The 3DR-FPGA-ADC-10GSPS is a 4 channel, 12 bit, 10 GSPS analog-to-digital converter board for digitizing and processing analog inputs. High performance, low latency processing can be implemented via the on-board Altera Arria 10 FPGA (10AX115U3F45I2SG).

As with all 3DR computing modules, the 3DR-FPGA-ADC-10GSPS supports three-dimensional connectivity, allowing the user to stack and/or tile modules to address a wide variety of processing, I/O, size, weight, and power requirements. The 3DR-FPGA-ADC-10GSPS provides PCIe and LVDS interfaces via the Y and Z connectors to other modules in the 3DR computing family. It also offers additional external interfaces including TwinAx, and SMA connections for clocking and triggering flexibility along with Time of Day (ToD).

3DR computing technology brings together high performance computing, ease of programmability, low cost, and commercial I/O flexibility in a modular, open systems and standards architecture to realize uniquely scalable and widely configurable, high speed embedded processing solutions for the development of radar, EW, SIGINT, and communication systems. 3DR computing possesses the unique ability to morph in size, shape, and processing capacity. This flexibility provides a low cost, standard solution capable of rapidly conforming to the vastly different power, space, and environmental requirements found aboard any surface, sub-surface, or airborne system or platform.

  • 4 Channel, 2.5 GSPS Non-Interleaved ADC, >8 ENOB
  • 2 Channel, 5 GSPS Interleaved ADC, >8 ENOB *
  • 1 Channel, 10 GSPS Interleaved ADC, >8 ENOB *
    * Requires interleaving board


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  • Digital Signal Processing/Data Acquisition
  • Radar Receiver (Digital Receiver)
  • Digital Array Processing & Beamforming
  • Electronic Warfare/Attack Systems



  • Altera Arria 10
  • 10AX115U3F45I2SG
  • 2x—Hybrid Memory Cube (HMC)

Analog-to-Digital Conversion

  • 4×2.5 GSPS Channels Non-Interleaved
  • 2×5 GSPS Channels Interleaved
  • 1×10 GSPS Channel Interleaved
  • 12-bit
  • >8 ENOB
  • Non-Linear Equalizer IP
  • >4 GHz Instantaneous Bandwidth

Clocking and Triggering Flexibility

  • Sample Gates (SMA)
  • Trigger (SMA)
  • Clock Inputs (SMA/TwinAx)
  • ToD—Time of Day

I/O Support available Via:

  • Y-Connector (2x)
  • Z-Connector (1x)
  • High Speed Connector (1x Top)
  • JTAG
  • 4x—40 GbE Daughter Card

Product Benefits

  • Enough FPGA Flash memory to hold two FPGA configurations
  • On board circuitry, fuse and temperature monitoring for board protection
  • Standard 4-pin power connector


Memory – HMC

  • 4/8 GB RAM
  • 70% Less Power and up to 17X Faster than DDR3

Health Monitoring

  • Board Voltages
  • Temperature of K61, PCIe switch, FPGA
  • Two external temperature sensors
  • I2C


  • Power Consumption: 12V @ 15.5 Amps (Subject to FPGA Loading)
  • Supply Options: 12V Power Cable
  • Additional Power Features: E-fuse/Continuous Power Monitoring